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By Ojeda J.L., Cristobal J.A.

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Evaluation is done on a set of parallel NAS applications. Keywords: Cell BE Architecture, Software Cache, Pre-fetching, Modulo Scheduling. 1 Introduction Heterogeneity has become one particular trend in recently proposed computer systems. For instance, the IBM Cell BE processor [1-5] is a multi-core design that mixes two architectures: a traditional superscalar core based on the PowerPC architecture surrounded by eight cores based on the Synergistic Processor Element (SPE)[4]. In the IBM Cell architecture, the SPEs are provided with local memories and data transfers from/to main memory are explicitly performed under software control.

In the case of CG-B, the improvements range from 3% up to 10 % at most. Loops 3 and 7 suffer from slight degradation (not even a 1% and 5% respectively). The reason for that is related to the differences on how deeply the loops are affected by communications. The CG-B loop 9 is dominated with irregular memory references and is the most consuming loop in the CG-B. Improvement achieved in this loop has 44 N. Vujić et al. good influence on overall execution time of the CG-B (Figure 7). The case of the ISB is different.

It contains 3 elements; the global base address of the original reference, the local base address in the cache storage, and a pointer to the cache line descriptor. We implement an efficient, fully associative cache structure using the Cache Directory structure. It contains a sufficiently large number of double–linked lists (128 lookup(g5) Cache line descriptors g5 lookup(g3) Cache State 7 … L8 15 L15 16 L16 23 L23 Global addr: g5 24 L24 Local data addr: l2 31 Turn Ticket Translation Record Global addr: g3 Local data addr: l7 … Last L7 … First g3 8 … l4 Free links Cache Directory Directory links … … l2 DMA Tags … Ref counter Placement Index L0 … l7 0 … State (modif…) Translation Record Unused List Cache Storage Local data addr: l2 … Cache Directory Global addr: Cache Storage L31 Cache line descriptor Cache param.

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